1. Technical Field
The present invention relates to a system and method for re-executing test patterns in varying timing scenarios for processor design and verification. More particularly, the present invention relates to a system and method of re-executing test patterns at different initial cache line memory states, which creates different timing scenarios when the processor executes the test patterns.
2. Description of the Related Art
A processor test team typically employs test patterns in order to verify and validate a system design. Processor testing tools exist whose goal is to generate the most stressful test pattern for a processor. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test patterns.
Verifying and validating a processor using test patterns typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. A challenge found is that the test pattern build stage is typically the most time consuming process in any verification process, which overshadows the actual time spent on test pattern execution. As a result, little time is left for test pattern execution and validation/verification stages.
What is needed, therefore, is a system and method that reduces test pattern build times in order to allocate more time for test pattern execution and validation/verification stages.